OVI Verilog Analog Mixed-Signal Group

The Verilog-AMS Technical Subcommittee has been created under the auspices of Open Verilog International (OVI) with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language. This activity has resulted in the OVI approval of the Verilog-A LRM in June of 1996 and Verilog-AMS LRM in August of 1998 which now supersedes the Verilog-A LRM. Verilog-AMS benefits users by allowing them to describe and simulate analog and mixed signal designs using a top-level design methodology as well as the traditional bottom up approaches. OVI's Verilog-AMS standard supports analog and mixed signal designs at three levels: transistor/gate, transistor/gate-rtl/behavioral, and mixed transistor/gate-rtl/behavioral circuit levels.
Moreover, Verilog-AMS provides powerful structural and behavioral modeling capabilities for systems in which the effects of, and interactions among, different disciplines like electrical, mechanical and thermal are important.

The goal of this web site is to make sure that analog, mixed signal and system designers can find relevant information on the Verilog-AMS, from activities to technical data on how to better use these extensions.