Francisco Barat, ESAT, KULeuven, Belgium, 2005

Over the last couple of years, the demand for portable multimedia
devices has been growing at an impressive rate. The ideal multimedia
device will present high quality multimedia content, and will be
networked, portable, inexpensive and easy to use. In order to cope with
the dynamism of current and future multimedia applications, it will be
based on one or more programmable processors specially designed for the
application domain.

Realizing this device requires an amazing increase in processor's
computing power while keeping the energy consumption growth at a
minimum. The purpose of this dissertation is to prove that widening a
very long instruction word (VLIW) processor can be an effective way to
improve the energy efficiency of multimedia applications if the adequate
architectural and compilation techniques are used to overcome the
scaling limitations of VLIW processors. The basis for this argument is
the existence of sufficient instruction-level parallelism in multimedia
applications and the possibility to exploit it efficiently with a
well-matched VLIW architecture.

To prove this thesis, this dissertation presents and evaluates the
coarse-grained reconfigurable instruction set processor (CRISP)
architecture and its compiler. The CRISP architecture is an evolution of
VLIW processors obtained by cross-breeding clustered VLIW architectures
and reconfigurable instruction set processors. Its foundation are a
clustered data-path with support for predication and two novel
architectural features, namely an instruction fetch path with scalable
bandwidth, and software controlled functional unit chaining.

The CRISP architecture, being a parameterized processor template,
requires a complete design space exploration flow to determine the
optimal values of the different parameters of the architecture as a
function of the application domain. This dissertation also addresses
this problem by presenting an extensible design space exploration framework.